With advantages of compact size, light weight, high image quality, low driving voltage, and low power consumption, thin film transistor plane displays have been widely used in electrical products such as portable computers, mobile phones, personal digital assistants, and color televisions, and have become the mainstream display apparatus.
The driving system of the thin film transistor plane display comprises source drivers and scan drivers, and the source drivers and the scan drivers include shift register circuits composed of a plurality of shift registers connected in series. Reference is made to FIG. 1 illustrating a diagram of a conventional PMOS (P-Channel Metal Oxide Semiconductor) shift register. The conventional shift register comprises a phase-shifting element 110 and a pull-high element 120. The phase-shifting element 110 is coupled to an input 112, a first clock node C1 and a second clock node C2, wherein the input 112, the first clock node C1 and the second clock node C2 are used for receiving an input signal, a first clock signal and a second clock signal, respectively. The pull-high element 120 is coupled to the phase-shifting element 110 and an output 124, and the output 124 outputs an output signal. The phase-shifting element 110 comprises a first transistor MP1 and a second transistor MP2, and the pull-high element 120 comprises an inverter 122 and a third transistor MP3. The drain of the first transistor MP1 and the gate of the second transistor MP2 are coupled to the input of the inverter 122 as a first node VX, and the output of the inverter 122 is coupled to the gate of the third transistor MP3 as a second node VY. The drain of the third transistor MP3 is coupled to a first voltage source (VDD) of high logic level. The output 124 is located on the node (not shown) of the drain of the second transistor MP2 and the source of the third transistor MP3. There is a boost capacitor (C_boost) between the first node VX and the second clock node C2.
The main function of the inverter 122 in the pull-high element 120 is to provide a proper logic level for the third transistor MP3 to enable the third transistor MP3 to output a proper signal of high logic level. Reference is made to FIGS. 2a, 2b, 3a, and 3b. FIGS. 2a and 3a illustrate diagrams of the structure of two types of the conventional inverters. FIGS. 2b and 3b illustrate timing diagrams of the two types of the conventional inverters. Input signals 210 and 226 are inputted to the two types of the conventional inverters, and the two types of the conventional inverters output signals 212 and 228, respectively. Since single transistor technique is used in the embodiments of the two types of the conventional inverters, when input signals 210 and 226 are of low logic level, the transistors 204 and 220 in the two types of the inverters are turned on to generate drain current signals 214 and 230. When the transistors 204 and 220 are under small signal analysis in AC voltage, there is drain-source resistance rds (not shown), so a current path is generated resulting in power consumption.
Moreover, the logic levels of the node signals of the first node VX and the second node VY may not be high enough to cut off the second transistor MP2 or the third transistor MP3. Or, the logic levels of the node signals of the first node VX and the second node VY may not be low enough to turn on the second transistor MP2 or the third transistor MP3. Thus results in the malfunctions of the second transistor MP2 or the third transistor MP3, which makes the conventional inverter generate wrong output signals.
Therefore, it is necessary to propose a method for the shift register circuit to solve the problem of power consumption described above, and further to enable the shift register circuit to output proper signals of high or low logic level without resulting in the malfunctions of the elements.